1. Field of the Invention
The present invention relates to a liquid crystal display unit, and more particularly to a structure of a liquid crystal display unit and fabricating method thereof which can raise the fabrication yield by reducing the number of mask processes.
2. Discussion of the Related Art
If there are large number of mask processes in the fabrication of a liquid crystal display unit, the fabrication yield is reduced and the fabrication cost is high since the mask process time is lengthy. Recently, techniques for reducing the number of mask processes in fabricating the liquid crystal display unit have been proposed.
FIG. 1 illustrates a structure of a conventional liquid crystal display unit. The conventional liquid crystal display unit includes a substrate 1, a gate electrode 2 formed on the substrate 1, a gate insulating layer 3 formed on the exposed surface of the substrate 1 including the gate electrode 2, an intrinsic semiconductor layer 4 and an impurity semiconductor layer 5 formed on the gate insulating layer 3, source and drain electrodes 6 and 7 formed on the impurity semiconductor layer 5 and separated by the channel length, a passivation layer 8 formed on the source and drain electrodes 6 and 7 and the exposed surface of the gate insulating layer 3, and a pixel electrode 10 formed on the passivation layer 8 and connected to the drain electrode 7.
FIGS. 2a to 2e illustrate layout views and fabricating processes of the conventional liquid crystal display unit of FIG. 1.
Referring to FIG. 2a, a metal material is deposited on the glass substrate 1 and selectively removed by a photolithographic process and an etching process to form the gate electrode 2 for driving an active layer. Although not shown in the drawing, a storage capacitor electrode, a source pad and a gate pad are simultaneously formed when forming the gate electrode 2.
Next, as shown in FIG. 2b, an oxide layer or a nitride layer is deposited on the entire surface of the substrate 1 including the gate electrode 2 to form the gate insulating layer 3. The amorphous silicon layer 4 for forming the active layer is formed on the gate insulating layer 3. The n+ amorphous silicon layer 5 is formed on the amorphous silicon layer 4 in consideration of a contact resistance between the active layer and the source and drain electrodes formed in a subsequent process. The n+ amorphous silicon layer 5 and the amorphous silicon layer 4 are selectively removed by exposure and development using an active region pattern mask.
Referring to FIG. 2C, a metal material is deposited on the entire surface of the substrate 1 and selectively removed by the photolithographic process to form the source and drain electrodes 6 and 7. The n+ amorphous silicon layer 5 on the channel region is selectively removed by the exposure and development using the source and drain electrodes 6 and 7 as a mask.
Referring to FIG. 2d, the passivation layer 8 is deposited on the entire surface of the substrate 1 including the source and drain electrodes 6 and 7 and selectively removed until a portion of the drain electrode 7 is exposed to form a contact hole 9.
Referring to FIG. 2e, an ITO (indium/tin/oxide) layer is deposited on the entire surface of the substrate 1 electrically connected to the drain electrode 7 through the contact hole 9. The ITO layer is then selectively removed to form the pixel electrode 10.
Thus, the fabrication of a transistor in the liquid crystal display unit is completed through five mask processes. Meanwhile, although not shown in the drawings, an additional mask process is required to expose the source pad and the gate pad, as well as five mask processes for the gate electrode, semiconductor layer, source and drain electrodes, contact hole and pixel electrode.
As previously noted, since five or more mask processes are needed to fabricate the liquid crystal display unit, the fabrication process is complicated and the fabrication time is increased. Hence, the fabrication yield is reduced and the fabrication cost is increased.